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Codasip, RISC-V Custom Compute specialist, now offers Siemens EDA’s Tessent Enhanced Trace Encoder product with its customisable RISC-V cores, allowing
Codasip, a leader in RISC-V Custom Compute, is now offering the Tessent Enhanced Trace Encoder solution from the Tessent Embedded Analytics product line at Siemens EDA with its customisable RISC-V cores.
Codasip® now offers the Tessent™ Enhanced Trace Encoder solution from the Tessent Embedded Analytics product line at Siemens EDA with its customizable RISC-V cores. Through the joint solution, developers can efficiently trace and debug issues between silicon and software, and accurately understand real-time behaviors of even the most complex customized designs based on Codasip RISC-V processors™.
The Tessent Enhanced Trace Encoder is the market-leading trace solution for RISC-V. It is a fully‑featured solution that provides a mechanism to monitor ...