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Pentek Ships Quartz RFSoC Rugged Small Form Factor Subsystem Ideal for Custom Integrations

Pentek Quartz Architecture with Xilinx Zynq UltraScale+ RFSoC FPGA
· Eight wideband RF/IF A/D and D/A converters
· Conduction-cooled and ideal for integration into custom enclosures
· Navigator Design Suite for streamlined software and IP development
Embedded TechTrends─January 25, 2021─Pentek, Inc., today introduced additions to the Quartz® RFSoC Architecture family, the Model 6350S and Model 6353S (Gen 3 RFSoC), eight-channel A/D and D/A converter subsystems in rugged small form factor package. Based on Pentek QuartzXM eXpress modules that utilize the Xilinx Zynq® UltraScale+ RFSoC FPGA, the Model 6350S and Model 6353S are very suitable for SIGINT and COMINT, military communications, EW countermeasures, radar transceiver, test and measurement, SATCOM, LiDAR, 5G and LTE wireless applications. ....

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Pentek Announces Immediate Availability of Higher Bandwidth Gen 3 RFSoC Solutions

Pentek Announces Immediate Availability of Higher Bandwidth Gen 3 RFSoC Solutions
PR.com
2020-12-31
Upper Saddle River, NJ, December 31, 2020 (PR.com) Pentek, Inc. today announced extensions to their proven Quartz® RFSoC product family by introducing the QuartzXM eXpress Module, the Model 6003, adding greater RF performance and scalability. The QuartzXM Model 6003, based on the Xilinx Zynq® UltraScale+™ RFSoC Gen 3, provides full sub-6 GHz direct-RF I/O support and greater flexibility with more decimation and interpolation options. The QuartzXM Model 6003 is ideal for 5G and LTE wireless, SIGINT, EW, communications and radar applications in SWaP-critical environments.
Immediately releasing products utilizing Xilinx Zynq UltraScale+ RFSoC Gen 3 demonstrates our commitment to offering our customers the latest technology for their applications,” said Bob Sgandurra, Pentek’s director of Product Management. “The modularity of our Quartz product lin ....

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Advancing HLS Adoption – Xilinx, Silexica, Falcon

Facilitating Abstract Hardware Design
by Kevin Morris
The history of digital hardware design is one of managing ever-increasing complexity by raising the level of design abstraction. When our digital circuits had four inputs, it was completely reasonable to do logic minimization with a Karnaugh map. When sequential logic was involved, a state diagram was a nice way to work things out, and we could generally draw a single page schematic with a dozen or so logic gates describing our implementation. As the number of logic gates soared, though, those schematics became hundreds of incomprehensible pages.
We leveled up, of course, and adopted register-transfer level design and logic synthesis. At that higher level of abstraction, we could describe tens of thousands of gates of logic with just a few hundred lines of hardware description language. The downside, of course, was that we were now separated from the “bare metal” of the logic gates in our des ....

Jason Cong , Xilinx Vivado , Xilinx Vitis Unified Software Platform , Falcon Computing Solutions , Vitis Unified Software , Neptune Design Automation , ஜேசன் காங் , ஃபால்கன் கணினி தீர்வுகள் , நெப்டியூன் வடிவமைப்பு ஆட்டோமேஷன் ,