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Imperas updates Free reference model riscvOVPsimPlus with new RISC-V P (SIMD/DSP) extension and Architectural Validation Test Suites


Posted July 19th, 2021 for Imperas
Imperas simulation technology and reference model available for free, including test suites for basic processor hardware verification and compliance testing.
Oxford, UK – July 19th, 2021  – Imperas Software Ltd ., the leader in RISC-V processor verification technology, announces the latest updates to
riscvOVPsimPlus with support for the near ratified P extension and architectural validation test suites. The P (or Packed SIMD/DSP) extension is a significant addition to the flexibility of the modular RISC-V ISA (Instruction Set Architecture); it supports real-time data processing applications as part of the main processor pipeline without the need for the associated inefficiencies of a co-processor. For processor hardware verification, a basic test suite helps ensure implementations have a basic software level compatibility to the new P extension as a reference to the developers’ interpretation of the written specificatio ....

United Kingdom , Simon Davidmann , Chuanhua Chang , Wei Wu , Riscv Internationalp Extension Task Group , Imperas Software Ltd , Andes Technology Corporation , Imperas Software , Instruction Set Architecture , Instruction Set Simulator , Architectural Validation Test Suites , Open Virtual Platforms , Cadence Palladium , Imperas Software Limited , ஒன்றுபட்டது கிஂக்டம் , வெய் வு , அண்டெஸ் தொழில்நுட்பம் நிறுவனம் , அறிவுறுத்தல் அமை கட்டிடக்கலை , அறிவுறுத்தல் அமை சிமுலேட்டர் , திறந்த மெய்நிகர் தளங்கள் , கேடென்ஸ் பல்லேடியம் ,