Cadence Accelerates Hyperscale SoC Design with Next-Generation 112G Extended Long-Reach SerDes IP on TSMC's N4P Process

Highlights:



DSP-based, flexible-rate SerDes IP is optimized for PPA for next-generation cloud networking, AI/ML, and 5G wireless applications



New architecture delivers exceptional ELR... | April 24, 2023

Related Keywords

Sanjive Agarwala ,Dan Kochpatcharin ,Cadence Design Systems Inc ,Design Infrastructure Management Division ,Ip Group At Cadence ,Asics ,Nasdaq ,Companies To Work ,Cadence Design Systems ,Extended Long Reach ,Medium Reach ,Very Short Reach ,Cadence Intelligent System ,Intelligent System Design ,Nc Stock Exchange ,News ,Information ,Press Release ,Verdes ,P ,Us ,Optimized ,Or ,Pa ,Cloud ,End ,G ,Ireless ,Architecture ,Elivers ,Xceptional Cdns Us1273871087 ,