Imperas updates RISC-V verification software
The latest addition to the Imperas RISC-V Verification IP (VIP) software has Floating-Point architectural validation test suites covering the RISC-V Specifications for 32bit Single-Precision (32F), 64bit Single-Precision (64F), and 64bit Double-Precision (64D).
These tests extend the current Imperas range of tests for ratified and near-ratified specifications tests.
The latest RISC-V verification ‘step-and-compare’ methodology can be used to verify an RTL processor implementation against the Imperas golden reference model in a SystemVerilog UVM environment.
This covers asynchronous events and offers a transition to debug analysis when an issue is found. More details on test benches with Imperas RISC-V verification reference models are available at https://www.imperas.com/riscv.