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Imperas updates RISC-V verification software The latest addition to the Imperas RISC-V Verification IP (VIP) software has Floating-Point architectural validation test suites covering the RISC-V Specifications for 32bit Single-Precision (32F), 64bit Single-Precision (64F), and 64bit Double-Precision (64D). These tests extend the current Imperas range of tests for ratified and near-ratified specifications tests. The latest RISC-V verification ‘step-and-compare’ methodology can be used to verify an RTL processor implementation against the Imperas golden reference model in a SystemVerilog UVM...

Imperas Leads The RISC-V Processor Verification Ecosystem Verification IP extended with Floating-Point architectural validation test suites based on golden reference model and coverage-based development. Oxford, United Kingdom, January 25th, 2021 — Imperas Software Ltd., the leader in RISC-V processor verification technology, today announced the latest addition to the Imperas RISC-V Verification IP (VIP) solutions with the Floating-Point architectural validation test suites covering the RISC-V Specifications for 32bit Single-Precision (32F), 64bit Single-Precision (64F), and 64bit Double-P...