Page 3 - Imperas Software News Today

Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced that Andes Technology Corp., a leading supplier of performance-efficient and extensible 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, has certified the Imperas reference models for the complete range of Andes processor IPs with Andes Custom Extension™ (ACE) support and the…

Imperas Software, a developer of RISC-V simulation solutions, has announced that Andes Technology, a supplier of 32/64-bit RISC-V processor cores, has certified Imperas reference models.

In this article we try to provide you design software/tools companies offering product and support service to RISC-V based chip designs from small companies to biggest chip design experts such as Intel.

Imperas Software has entered into a strategic alliance with Intel regarding Intel Pathfinder for RISC-V.

Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced a strategic alliance with Intel® regarding Intel® Pathfinder for RISC-V1. Imperas has designed an integrated reference model and simulator as a fixed platform kit to support the growing ecosystem of RISC V. Imperas models are the established reference for RISC V and are now included…

Imperas Software has announced the release of the first open-source SystemVerilog RISC-V processor functional coverage library for RISC-V cores.

Imperas Software, a supplier of RISC-V simulation solutions, has announced updates for RVVI (RISC-V Verification Interface) for RISC-V processor verification with virtual peripherals to support asynchronous events and system level interrupts.

Imperas Software, a supplier of RISC-V simulation solutions, has announced the latest RISC-V test suites and updates to the free riscvOVPsimPlus reference model, simulator and test suites.

Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced a partnership with Breker Verification Systems, a leading provider of advanced test content synthesis solutions for SoC, UVM and Post-Silicon verification environments. With a combined approach to standards-based verification, development teams will be able to efficiently transition from RISC-V processor functional design verification (DV) right…

RISC-V simulation company Imperas Software has announced a partnership with Breker Verification Systems, a provider of test content synthesis for