Page 5 - Imperas Software News Today

Oxford, United Kingdom, November 29th, 2021 — Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced with MIPS, Inc., the processor technology company focused on the commercialization of RISC-based processor architectures and IP cores, the continuation and extension to the long-standing relationship with simulation and verification support for RISC-V. Since 2010, MIPS has partnered with Imperas…

Oxford, United Kingdom, October 18th, 2021 - Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced Razorcat Developments, a leading provider of software testing tools for the embedded systems market, has integrated the Imperas fast processor reference models into the popular TESSY environment for embedded software testing. Embedded software development requires rigorous…

Posted July 19th, 2021 for Imperas Imperas simulation technology and reference model available for free, including test suites for basic processor hardware verification and compliance testing. Oxford, UK – July 19th, 2021  – Imperas Software Ltd ., the leader in RISC-V processor verification technology, announces the latest updates to riscvOVPsimPlus with support for the near ratified P extension and architectural validation test suites. The P (or Packed SIMD/DSP) extension is a si...

Andes certifies Imperas RISC-V Reference Models for SIMD/DSP extension Imperas Software has announced that Andes Technology, a supplier of 32/64-bit RISC-V CPU cores and a member of the RISC-V International Association, has certified the Imperas reference models for the complete range of Andes IP cores with the new RISC-V P extension. As a consequence, developers will now be able to use the Imperas reference models to evaluate multicore design configuration options for S...

SiFive collaborates with Imperas, qualifies models Imperas Software, a specialist in virtual platforms and high-performance software simulation, has announced that SiFive, the industry leader in RISC-V processors and silicon solutions, has qualified its models for the full range of the SiFive processor Core IP Portfolio. Simulation models are an essential starting point for early SoC architectural exploration, as system designers use virtual platforms to test full applic...

Imperas extends RISC-V processor verification ecosystem Imperas Software, a specialist in RISC-V processor verification technology, has announced the latest addition to its suite of RISC-V Verification IP (VIP) solutions. This solution includes Floating-Point architectural validation test suites covering the RISC-V Specifications for 32bit Single-Precision (32F), 64bit Single-Precision (64F), and 64bit Double-Precision (64D). The tests are designed to extend the company...

Imperas Leads The RISC-V Processor Verification Ecosystem Verification IP extended with Floating-Point architectural validation test suites based on golden reference model and coverage-based development. Oxford, United Kingdom, January 25th, 2021 — Imperas Software Ltd., the leader in RISC-V processor verification technology, today announced the latest addition to the Imperas RISC-V Verification IP (VIP) solutions with the Floating-Point architectural validation test suites covering the RISC...

Imperas is providing free simulator, architectural validation test suites and SystemVerilog components for verifying RISC-V system-on-chip designs