Page 148 - P Core News Today

Arasan Chip Systems, the leading provider of IP for Mobile Storage Standards, presents its latest xSPI Master IP for access to NOR Flash Devices. This ...

NeuPro-S™ is a low power AI processor architecture for on-device deep learning inferencing, imaging and computer vision workloads. While NeuPro-S ...

The demand for advanced multimedia features is pushing device manufacturers to integrate more advanced peripherals such as multi-megapixel cameras and ...

This pipelined ADC can be applied for up to 20MSps sampling frequencies. By using interleaved switched-capacitor circuitries a CLK signal with half ...

The INNOSILICON USB 2.0 OTG PHY is fully compliant with UTMI+ level 3 Rev 1.0 specification. Offering excellent performance combined with a die size up ...

The TSN End Node IP core from NetTimeLogic is a standalone Time Sensitive Networking (TSN) single port end node core according to IEEE 802.1 and IEEE ...

VaultIP is a Silicon IP Secure Element adding 360° security to mobile processors. It protects against an increasing number of sophisticated threats ...

IEEE 802.11p is an approved amendment to the IEEE 802.11 standard to add wireless access in vehicular environments (WAVE), a vehicular communication system. ...

SM4 (former name “SMS4”) is a cryptographic standard published by the Office of State Commercial Cryptography Administration (OSCCA) of SCA as an ...

The MXL-D-PHY-UNIV-T-65GP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for ...