Page 146 - P Core News Today

The MIPI RFFE Master Controller IP Core is a full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. ...

Synopsys DesignWare USB-C 3.0 and USB 3.0 PHY IP provide designers with the industrys best combination of low area and low power with support for the ...

The MXL-PHY-CSI2-RX+ is a high-frequency low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Alliance Standard for D-PHY. ...

Safe Connect Systems (SCS) IP Cores allow to design full deterministic TSN critical applications with a full range of undisputed assets: • TSN stack ...

This MIPI DPHY/LVDS Combo Tx PHY IP is designed to the MIPI D-PHY 1.2 specifications and LVDS specifications. This IP supports up to 1.5Gbps for both ...

The TLS handshake hardware accelerator is a secure connection engine that can be used to offload the compute intensive Public Key operations (Diffie-Helmann, ...

The BLE5ZSUBGS40LP RF IP is designed for SMIC 40nm LP Process. It is a cost-effective low power dual-band communication sub-system. It integrates TX/RX ...

CEVAs RivieraWaves Bluetooth 5.2 Low Energy IP is a comprehensive and flexible solution for integration into SoCs/ASSPs. The RW-BLE hardware baseband ...

The MXL-CPHY-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY can be configured as a MIPI Master or MIPI ...

SureCore’s EverOn™ Single Port Synchronous Ultra Low Voltage SRAM IP combines high-density foundry bitcells with sureCore’s low-voltage and low-power ...