Page 144 - P Core News Today

The Public Key Crypto Engine is a versatile IP core for hardware offloading of all asymmetric cryptographic operations. It enables any SoC, ASIC and FPGA ...

The JPEG-LS-E core implements a highly-efficient, low-power, lossless and near-lossless image compression engine that is compliant to the JPEG-LS, ISO/IEC ...

The RapidIO Controller solution (GRIO) is a highly flexible and configurable IP. The The RapidIO Controller can be used as a Host or device. The RapidIO Controller when used along with the RapidIO to AXI Bridge (RAB) provides speed multi-channel DMA, Data Message and Data streaming functionality to match the bandwidth requirements of the RapidIO interface.

Mobile Semiconductor s Trailblaze(TM) software delivers silicon-proven SRAM compilers to generate low voltage (LV), ultra high speed (UHS), multi-megabit ...

The USB 2.0 Host Controller core (GRUSBHC) provides a link between the AMBA on-chip bus and the Universal Serial Bus (USB). The host controller supports ...

IQonIC Works USB-C/PD power adapter IP includes components required to build an integrated programmable power supply (PPS) charger solution. The USB ...

The World’s First Acceleration Structure Generation H/W for Powerful Dynamic Real-time Ray Tracing Implementation RayTree is a dedicated KD-tree ...

The Synopsys DesignWare® DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) ...

DesignWare® DDR Memory Interface IP is a family of complete system-level IP solutions for system-on-chips (SoCs) requiring an interface to one or more ...

The ultra-low-power RF transceiver is designed to meet standards such as Bluetooth Low Energy (Bluetooth Smart), 802.15.4 PHY Layer (e.g. ZigBee), and proprietary standards with data-rates from 62.5 kBit/s up to 4 Mbit/s.