Page 143 - P Core News Today

A full suite of embedded monitoring IP managed by a PVT controller with standard interfaces, creates a complete subsystem dedicated to maximizing performance, ...

The MXL-DPHY-DSI-TX+ is a high-frequency low-power, source-synchronous, physical layer supporting the MIPI Alliance Specification for D-PHY v2.1, which ...

The Arasan USB 2.0 Hub IP core is an USB 2.0 specification compliant hub core that supports 480 Mbit/s in High Speed (HS) mode, 12 Mbit/s in Full Speed ...

The Innosilicon Multi-SERDES PHY is a highly configurable design that supports SATA3, PCIe2, USB3.0 and XAUI with full compliance. It is available in ...

CEVAs RivieraWaves Bluetooth 5.2 dual mode IP is a complete and flexible solution for integration into SoCs/ASSPs. It contains both "classic" BR/EDR ...

The BA51 is a highly configurable, low-power deeply embedded RISC-V processor IP core. It implements a single-issue, in-order, 2-stage execution pipeline, ...

The AL-E215 is Allegro DVT’s second generation AV1 video encoder IP supporting real-time and file-based encoding. Built upon a true multi-format architecture, ...

BiDirectional LVDS IO circuit combines LVDS driver and receiver circuits to enable a single pair of IO pads to function as a 1.5Gbps bi-directional LVDS ...

The MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v1.2. ...

Allegro DVT’s AL-E210 is the first video encoder IP to implement real-time and file-based encoding in AV1 format. Built upon a true multi-format architecture, ...