Page 145 - P Core News Today

The multi-channel DesignWare® PHY IP for PCI Express® (PCIe®) 5.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands ...

The Apodis IPL4002M OTN processors ASICs are a member of Tera-Pass’ product family for access applications. Apodis IPL4002M processors support the functionality ...

The Cadence® Tensilica® HiFi 1 DSP is the smallest and lowest power member of the HiFi DSP family, developed for battery-constrained applications, such ...

The DesignWare Mixed-Signal PHY IP for SATA and eSATA is designed for use in SoC solutions. The PHY integrates seamlessly with the DesignWare SATA AHCI ...

The Western Digital SweRV Core™ EL2 is a single issue, RV32IMC, single-issue core with a 4-stage in-order pipeline. Like the EH1 and EH2, it supports ...

WhisPro is a neural network based speech recognition software package, allowing customers to add voice activation to voice-enabled IoT devices. WhisPro™ ...

This high-speed Digital-to-Analog Converter (DAC) IP block is implemented with fully differential single channel output specifically designed for crystal ...

The Analog-Frontend (AFE) IP consists of programmable current and voltage preamplifier followed by a Successive Approximation Register (SAR) architecture ...

The SweRV Core EH1 Support package (SCSP) contains everything needed to deploy a Western Digital SweRV™ EH1 core in an integrated circuit providing ...

Chips&Media’s Camera ISP IP – CARPO is the Imaging Signal Processing (ISP) targeted to be used in a low light environment for surveillance cameras, ...