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Northwest Logic Error Correction Coding (ECC) Core from Rambus implements the standard Hamming Code based DRAM Single Error Correction (SEC) and Double ...

Secure Clock IP core is a PRNG-based hardware implementation of a random clock jitter injection and/or a random clock cycle inhibition. It is intended ...

The SVTPlus-CSI2-F is a second generation MIPI CSI2-Tx transmitter IP core for FPGA implementations. It complies with MIPI® CSI2 V2.0 and DPHY1.2 specifications, ...

HIP 3500 is MIPI DSI Host (TX) IP core. HIP 3500 receives pixel data and commands from the host processor through AXI/AHB interface and sends data to ...

OpenFive’s PCS IP is fully compliant to the IEEE 802.3 standard supporting various MAC rates like 10G, 25G, 40G, 50G, 100G, 200G and 400G. Built ...

Comcores IP-core is a silicon agnostic implementation of the CPRI 6.1 standard targeting any ASIC, FPGA or ASSP technologies. With its extreme flexibility ...

XIP3323B from Xiphera is a versatile Intellectual Property (IP) core designed for SHA-384 cryptographic hash function with extended support for HMAC message ...

Designed for performance and power efficiency, the GDDR6 PHY enables big data analytics, crypto mining, ADAS, AI, machine learning, and deep learning. ...

The USB 2.0 High-Speed Host and Device Controller is a highly configurable, synthesizable USB core built from silicon-proven technology from NXP Semiconductors. ...

The Synopsys DesignWare® Few Time Programmable (FTP) Trim Non-Volatile Memory (NVM) IP provides the capability of reprogrammable NVM in a standard CMOS ...