Page 15 - P Core News Today

The Rambus Compute Express Link® (CXL®) 3.1 controller is a parameterizable design for ASIC and FPGA implementations. It leverages the Rambus PCIe® ...

NetTimeLogic’s Synchronous Ethernet (SyncE) Node is a full hardware (FPGA) only implementation of an ESMC frame Handler and State selector. The whole ...

Logic Fruit Technologies has designed FlexRay RTL IP Core, supporting data rate up to 10 Mbps. FlexRay, a high-speed protocol for advanced vehicles, ...

The ODT-LDO-IC-250M-12 is a low dropout (LDO), linear regulator for integration in a SoC. The LDO uses advanced control techniques to achieve excellent ...

The High-Bandwidth Memory generation 3 (HBM3) PHY is optimized for systems that require a high-bandwidth, low-latency memory solution. The memory subsystem ...

The ODT-ADS-12B2G-12 is a ultra-high performance 12-bit 2 GSPS ADC in a standard 12nm CMOS process, implemented using Omni Design's groundbreaking low ...

ESi-Kyber is a hardware accelerator core designed to accelerate post-quantum Key Encapsulation Mechanism (KEM) as defined by NIST FIPS 203. Kyber, ...

Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and networking ...

As part of Secure-IC's iSSP (integrated Security Service Platform), Secure-IC is able to provide integrated Secure Elements (iSE) that can act as trust ...

The SPD5 Hub function controller IP has been developed to interface I3C/I2C Host Bus and it allows an isolation of local devices like Temperature Sensor(TS), ...