Page 14 - P Core News Today

ESi-Dilithium is a hardware core for accelerating the high-level operations specified in the NIST FIPS 204 standard. Dilithium is an integral part ...

The Bitec HDCP IP Core is for use with the Bitec DP and HDMI IP cores. It is designed to ease the integration of content protection to FPGA and ASIC based ...

The EFLX®4K Tile is an embeddable standalone FPGA IP core, with 3 versions, that communicates with the rest of your SoC using input and output pins ...

The EFLX® 1K Logic IP tile is an eFPGA (embeddable FPGA) IP tile with power management containing 560 Look-Up-Tables (LUTs: each is 6-input, or dual-5-input, ...

The Keccak Hash crypto engine is an IP core and built with a focus on simplicity and seamless integration, while also following coding and verification ...

<b>The MACsec Engine implements the latest IEEE 802.1AE specification, providing connectionless data integrity, data origin authenticity and confidentiality ...

High performance, 12-bit resolution, 5-Msps sample rate Ultra Low Power Mixed-signal SAR ADC IP Core Node available in 28nm. Leading edge systems on chip ...

The Digital Blocks DB-DMAC-MC2-DL-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory ...

The Cadence Neo NPUs offer energy-efficient hardware-based AI engines that can be paired with any host processor for offloading artificial intelligence ...

The Bitec Camera Front End IP allows developers to interface CMOS and CCD cameras to an Altera FPGA. Using a memory optimised line buffer, the core sits ...