Page 16 - P Core News Today

Extoll’s SerDes architecture is based on digital design elements and methodologies. Plain analog blocks are only used where absolutely necessary. Various ...

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solution ...

DMP K3000 2D GPU IP Core offers the most powerful rendering performance in the industry, with a minimum area solution. You will witness blazing font and ...

The 28 Gbps Multi-Protocol SerDes (MPS) PHYs are comprehensive IP solutions that deliver enterprise-class performance across the challenging signaling ...

AON1010™ belongs to the highly optimized AONVoice™ Neural Network cores for Voice and Audio recognition. This solution is optimized for processing ...

Tessent Embedded Analytics accelerates debug, validation, and optimization of complex multi-core SoCs. Leveraging embedded non-intrusive instrumentation ...

Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high performance ...

The Digital Blocks DB-SPI-S-AMBA-BRIDGE is a Serial Port Interface (SPI) Controller Verilog IP Core supporting SPI Slave Interface to APB Master Bus. ...

The 16 Gbps Ethernet SerDes PHYs is a high-performance serial link subsystem. Optimized for power and area in challenging, high-loss channels typical ...

The AT64X8U55ULP6AA is organized as a 64-word by 8 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in 55nm ULP standard ...