DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List
The Digital Blocks DB-DMAC-MC2-DL-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory ...
Digital Blocks Multi Channel Scatter Gather Status Register Interface Axi4 Stream Interface Xi4 Memory Map Dma Controller
Source: design-reuse.com