Page 151 - P Core News Today

M31 PCIe 4.0 PHY IP provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications. The PCIe 4.0 IP supports ...

The MIPI D-PHY is compliant with the MIPI Alliance Standard for D-PHY.

The Universal Serial Bus Device Controller provides a USB 2.0 function interface accessible from an AMBA-AHB bus interface. The core must be connected ...

Mobiveil’s Enterprise Flash Controller (EFC) is a highly flexible and configurable design targeted for enterprise storage applications like SSD. The ...

CrossBar Resistive RAM (ReRAM) is a non-volatile memory (NVM) that can be integrated into any complementary metal-oxide semiconductor (CMOS) semiconductor ...

The accelerating expansion of the Internet of Things brings with it a comparably expanding threat model. The growing number of endpoints require strong ...

The Synopsys DesignWare® USB 3.0 femtoPHY and DesignWare® USB-C 3.0 femtoPHY provide designers with a complete physical (PHY) layer IP solution for ...

E2系列针对面积和功耗进行了高度优化，提供一流的性能。针对微控制器和嵌入式设备，E2内核可通过高效的2级流水线配置为小至13.5k gates，或通过3级流水线，硬件浮点，指令缓存等实现更高性能。借助SiFive Core Designer平台，E2系列处理器可以完全定制以满足您的特定要求。

The TPS3211MP OSU processor is an IP Core solution designed for Xilinx FPGAs. TPS3211MP processors accept 10x STM1/OC3/STM4/OC12/FE/GE, 8x E1/T1 and 6x ...

This JPEG compression IP core supports the Baseline Sequential DCT and the Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements ...