Page 153 - P Core News Today

The MIPI D-PHY Transmitter is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY.

Our 5th generation DisplayPort Transmitter Link Controller core supports DisplayPort 1.4 and embedded DisplayPort 1.4b features, including link rates ...

The MXL-DPHY-CSI2-RX-T-065LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. ...

D/AVE HD is a cost-efficient IP core family for 2D and 3D graphics applications. The variants of the core are available for FPGAs, ASICs and SOCs, specifically ...

CEVA-TeakLite-4 is a low-power, native 32-bit, variable 10-stage pipeline, fixed-point DSP architecture framework. The CEVA-TeakLite-4 is a fully synthesizable, ...

The eSecure IP is a single subsystem for RISC-V based SoC to address key security challenges, playing the role of root-of-trust. The module is highly ...

This datasheet present s the verification e nvironment of Comsis IEEE 802.11n PHY IP, including a SystemVerilog test bench. This environment allows 2x2 ...

LPDDR4 multiPHY: Compatible with JEDEC standard LPDDR4 SDRAMs up to 4,267 Mbps - Maximum data rate is process technology dependent - Compatible with JEDEC ...

The DesignWare® Cryptography Software Library offers a comprehensive suite of encryption and certificate processing functions for embedded applications. ...

With NeoPUF as the core, PUFrt provides a foundation of trust and security for the chip system. It also provides a 1024-bit identification code with the ...