Page 155 - P Core News Today

PMCC_PLL5GN40 is a PLL IP block which synthesizes low-jitter (<0.3ps RMS) 4.96GHz to 5.6GHz (5.28GHz typical) clock signals from the 620-700MHz reference ...

The highly granular DTS offers a significant area reduction in comparison to some standard in-chip thermal sensor solutions and supports high accuracy ...

Zhuhai Chuangfeixin (CFX) offers two proprietary OTP technologies and respective silicon IPs：One is Anti-fuse, the other is floating gate. CFX OTP ...

ESi-RISCs eSi-1600 16-bit RISC CPU IP core is an extremely small, low-cost and low-power processor ideal for integration into ASIC and/or FPGA designs. ...

The Synopsys DesignWare® USB 2.0 picoPHY provides designers with a complete physical (PHY) layer IP solution, designed for low power mobile and consumer ...

LEE Flash G2 (G2) is an innovative Flash IP offering unique features that no other Flash IP could offer. It is based on LEE Flash G1, which consists ...

The PowerVR Series9XM family features include: an advanced scalable compute cluster architecture; high efficiency compression technology including parameter ...

The PTP Hybrid Clock (HC) from NetTimeLogic is a combination of NetTimeLogics PTP Transparent Clock (TC) and PTP Ordinary Clock (OC). It adds the Sync ...

SPC (Synthesizable Programmable Core) is a soft FPGA core that is fully integrated into standard design flows and that allows the seamless implementation ...

Intrinsic ID Zign™ RNG is an embedded software IP solution that enables device manufacturers and designers to add a random number generator to their ...