Page 152 - P Core News Today

The Geon™ Secure Execution Processor is a low-power, 32-bit processor IP core with built-in protection of sensitive code and data. It uses two or more ...

TICO-XS encoder is a visually lossless and JPEG-XS compliant IP-core specifically designed for the industry. This revolutionary technology is extremely ...

The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock. ...

The New Wave Design and Verification sFPDP core provides a complete IP solution for the VITA 17.1-2003 sFPDP specification. sFPDP is a high-speed, low-overhead, ...

IEEE 802.11i is a Wireless Local Area Network standard in the IEEE 802.11 set of specifications. It is also labelled as WPA ™ (Wireless Protected Access) ...

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock ...

XpressCCIX™ is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The XpressCCIX Controller IP supports ...

The PVT Controller provides a standard digital interface to the embedded Process, Voltage and Temperature (PVT) sensing Sub-System used to increase System ...

- Baseline JPEG encoder/decoder described in RTL compliant with ISO/IEC 10918-1 - High speed processing with low clock frequency - Suitable for ...

The GigaBit Ethernet Media Access Controller (GRETH_GBIT) supports 10/100/1000 MBit speed in both full- and half-duplex operation. The dataflow is handled ...