MIPI D-PHY CSI-2 RX (Receiver) in TSMC 65LP
The MXL-DPHY-CSI-2-RX-T-065LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. ...
Source: design-reuse.com
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PCIe 5.0 PHY for SS8LPU
The multi-channel DesignWare® PHY IP for PCI Express® (PCIe®) 5.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands ...
Source: design-reuse.com
112Gbps Serdes USR & XSR IP Core
Multi-Gigabit/s serial transceivers are fast replacing older parallel interfaces in most of applications. The accelerating demand for higher data rates ...
Source: design-reuse.com
MIPI RFFE Master IP Core IP Core
The MIPI RFFE Master controller IP is a highly optimized and technology agnostic implementation of the MIPI RFFE v.3.1 standard targeting both ASIC and ...
Source: design-reuse.com
MIPI D-PHY CSI-2 TX (Transmitter) in GlobalFoundries 22FDX
The MXL-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY ...
Alliance Specification Physical Layer Camera Serial Interface Mipid Phy Mipid Phy Transmitter Cd Phy
Source: design-reuse.com
DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Command Stream List
The Digital Blocks DB-DMAC-MC2-CS-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory ...
Digital Blocks Multi Channel Scatter Gather Stream Interfaces Status Stream Axi4 Stream Interface Xi4 Memory Map
Source: design-reuse.com
Intrinsic ID Zign® 300 - Software implementation of SRAM PUF with symmetric & asymmetric cryptography + PKI
Root-of-trust (RoT) technology is becoming a requirement for securing connected devices, their data, and, by extension, the entire infrastructure with ...
Iot Security Key Generation Device Identity Random Numbers Key Management Ntrinsic Id Zign 300 Software Implementation Of Sram Puf With Symmetric Amp Asymmetric Cryptography Pki
Source: design-reuse.com
Transaction-aware embedded cybersecurity solution that can detect, block and record attacks, & prevent propagation
Next-generation hardware-based cybersecurity product that can be used to detect, block and record cyber-attacks in a broad range of applications – from ...
Bus Sentry Ransaction Aware Embedded Cybersecurity Solution That Can Detect Lock And Record Attacks Mp Prevent Propagation Bus Sentry P Core
Source: design-reuse.com
768x39 Bits OTP (One-Time Programmable) IP, TSMC 55ULP 0.9V–1.2V / 2.5V
The ATO0768X39TS055ULP4NA is organized as 768x39 one-time programmable (OTP). This is a type of non-volatile memory fabricated in TSMC 55nm LP 1.2V/2.5V ...
General Purpose Smc 55nm Ulp 68x39 Bits Otp One Time Programmable Ip Smc 55ulp 0 9v 1 2v 2 5v P Core Ilicon Ip
Source: design-reuse.com
4Kx32 Bits OTP (One-Time Programmable) IP, TSMC 40nm ULP 1.1V/2.5V Process
The AT4K32T40ULP7ZC is organized as 4K-bits by 32 one-time programmable (OTP). This is a type of non-volatile memory fabricated in TSMC 40nm ULP standard ...
Smc 40nm Kx32 Bits Otp One Time Programmable Ip Smc 40nm Ulp 1 1v 2 5v Process P Core Ilicon Ip Emiconductor Ip
Source: design-reuse.com