Page 47 - P Core News Today

The Catastrophic Trip Sensor has been specifically designed to protect against thermal runaway and comprises a central hub and a remote thermal sensor. ...

The MXL-DPHY-DSI-TX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI® Alliance Standard for D-PHY. The ...

Display Stream Compression offers inter-operable, visually lossless real-time, video compression to satisfy the emerging high bandwidth and high resolution ...

LeWiz makes available its ultra low-latency 10G Ethernet MAC for IP licensing - targeting low-latency applications such as those in the financial sector. ...

The Synopsys DesignWare® HDMI 2.1 TX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, ...

The Memory & Bus Protection IP Core module enables on-the-fly encryption/decryption and authentication to the external memory. It supports AHB/AXI ...

The Digital Blocks DB9000AXI LCD / OLED Display Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA AXI Protocol Interconnect ...

The DVB-S2 LDPC-BCH block is a powerful FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite.

Root-of-trust (RoT) technology is becoming a requirement for securing connected devices, their data, and, by extension, the entire infrastructure with ...

ETA-TC1 platform is a set of silicon IPs specifically designed for small Solar Panel Cells made by a single PV diode. ETA-TC1 is Integrating the Low ...