Page 49 - P Core News Today

The IP is a 16-bit, delta-sigma (ΔΣ), analog-to-digital converter (ADC). It comprises of a second-order discrete-time modulator followed by a third-order ...

TC5390 is a decoder IP Core compliant with the small block lengths coding scheme for UCI as defined by 3GPP 4G-LTE and 5G-NR specifications. A single ...

CEVA-XM6 is the 5th generation imaging and computer vision processor IP from CEVA, designed to bring deep learning and artificial intelligence capabilities ...

JPEG, Lossless JPEG, JPEG 2000, JPEG-LS, DSC 1.2b and CCSDS 122.0 image compression IP cores for ASIC or AMD-Xilinx, Efinix, Intel, Lattice and Microsemi FPGA and SoC designs.

High-Quality, Low-Latency, Baseline, Main and High profiles H.264 video encoder IP cores for ASIC or Intel, Lattice, Microsemi and Xilinx FPGA and SoC designs.

For scalable and area-efficient heterogeneous cache coherent systems. The Arteris IP Ncore Cache Coherent Interconnect IP offers unparalleled scalability, ...

<b>The Crypto Coprocessors are a hardware IP core platform that accelerates cryptographic operations in System-on-Chip (SoC) environment on FPGA or ASIC.</b> ...

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solution ...

The MXL-DPHY-CSI-2-RX+ is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY ...

The MXL-CDPHY-DSI-TX+-T-N05 is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for ...