Page 56 - P Core News Today

ARINC 429 IP Core implements ARINC 429 standard. IP Core contains Rx and Tx processing blocks, Controller Block, Internal Memory and External Memory Interfaces. ...

Ultra-Low-Power BLE RF IP is designed to support 2.4 GHz standards like Bluetooth Classic (BR/EDR), 802.15.4 PHY Layer (e.g., ZigBee), ANT, and proprietary ...

Using Rad Hard By Design standard cells and design guidelines the silicon-proven EFLX eFPGA is now available, to US Companies, in a Rad Hard by Design ...

RISC-V is an open source instruction set architecture developed by UC Berkeley and now being widely adopted throughout the industry. As a member of RISC-V ...

The AT256X8T40G6AA is organized as 256 bits by 8 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in TSMC 40nm G standard ...

The MXL-CD-PHY-CSIRX-T-N07 is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for ...

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solution ...

The MACsec Engine implements the latest IEEE 802.1AE specification, providing connectionless data integrity, data origin authenticity and confidentiality ...

The MXL-DPHY-DSI-RX is a high- frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The ...

MIPI DSI-2 (Display Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile device ...