Page 76 - P Core News Today

The HBM3/2E/2 IP is suitable for applications involving graphics, high-performance computing, high-end networking, and communications that require very ...

Worlds first audio DSP IP with RISC-V Vector processor architecture RiVAI-V1 is a dual-issue, Out-of-Order execution, 7-stage pipeline, 32-bit RISC-V ...

The MXL-CD-PHY-CSITX+-40LP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for ...

Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and networking ...

The RAR-eSR-qLR Retention Alternating Regulator combines two regulation sub-components: a high-efficiency switching regulator (eSR) and an ultra low quiescent ...

The Multiple I/O Library supports both 2.5V analog IO cells & 3.3V digital IO cells. Digital IO contains 5V tolerance, open-drain & OSC cells. This library ...

Algo-Logic Systems’ Ultra-Low-Latency (ULL) Exact Match Search Engine (EMSE) IP is latency-optimized Key-Value Store (KVS) system for Accelerated Finance ...

028SAM_LDO_04 is external-capacitor-based Linear Regulator in Samsung 28 FD-SOI to generate SoC voltage supply voltage. It contains two independently ...

M SQUARE PCI Express 4.0 PHY IP includes high-speed, highly-efficient and cost-effective transceiver to turbocharge today’s high performance and high ...

Chevin Technology’s 10G & 25G UDP/IP Offload Engine for FPGAs has low latency and bandwidth overhead, as it sends packets of data without confirming ...