Page 78 - P Core News Today

The SONET/SDH Concatenated/Non-concatenated STS-192/STM-64 core implements the STS-192 and STM-64 layer function of Telcordia GR-253-CORE/ITU-T G.707, ...

The DesignWare® SuperSpeed 3.2 USB IP solution is based on the USB 3.2 specification from the USB Implementer Forum. The USB 3.2 IP offering includes ...

Movellus TrueDigital CGMs were purposely built for SoCs. Applications such as datacenter CPUs, AI accelerators, aerospace, and automotive require higher ...

The Origin E8 is designed for applications where performance is a primary design goal, including automotive/ADAS and data center applications. Expedera’s ...

Synopsys DesignWare® DDR3/2 PHY cores are mixed-signal PHY IP cores that supply the complete physical interface to JEDEC standard DDR3 and DDR2 SDRAM ...

VYUsync’s H.264 1080p60, 4:2:2, 10-bit Decoder Core is a highly optimized, high resolution decompression engine targeted primarily at FPGAs. The leading ...

The WEA1015R130G is a complete broadband wireless microwave receiver front-end operating in the frequency band spanning from 10 GHz to 15 GHz. Implemented ...

The Synopsys DesignWare® DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring ...

TESIC RISC-V is a CC EAL5+ PP0084 ready secure element IP including a secure 32-bit RISC-V core and that is delivered as soft IP or hard macro for plug-and-play ...

Rambus’s DDR3 Controller Core offered by Rambus is designed for use in applications requiring high memory throughput, high clock rates and full programmability. ...