Page 81 - P Core News Today

Synopsys’ DesignWare® Controller IP for Bluetooth low energy, Thread, and Zigbee delivers secure, concurrent wireless connectivity for Internet of ...

THis controller supports Xccela open standard bus for digital interconnect and data communications suitable for Volatile and nonvolatile memories such ...

The HDMI Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol mapping/interleaving as specified by the HDMI 2.1 ...

RiVAI-R1 is a dual-issue, Out-of-Order execution, 7-stage pipeline, 32-bit RISC-V CPU core IP that supports the RV32IMFAC instruction sets, as well as ...

The fully integrated Physical Coding Sublayer (PCS), KR4 FEC and Media Access Controller (MAC) core for 25Gbps Ethernet applications are compliant with ...

The MXL-DPHY-CSI2-TX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The ...

The logiISP Image Signal Processing Pipeline IP core is an Ultra High Definition (UHD) ISP pipeline designed for digital processing and image quality ...

The configurable and scalable DesignWare Controller IP for PCI Express (PCIe) supports all required features of the PCI Express 5.0, 4.0, 3.1, 2.1, 1.1 ...

Cadence Tensilica ConnX 110 and ConnX 120 DSPs provide ultra-low power and a small footprint balanced with high performance for radar, lidar, and communications ...

This is a DPHY IP compliant to the “MIPI Alliance Spec for C-PHY v2.1 and D-PHY v3.0”, which consists of 1-Clock and 4-Data lanes. It can support ...