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Audio I2S-TDM Transceiver The IObundle I 2 S/TDM Transceiver core is a configurable audio interface core with transmission and receiving capabilities. It supports master/slave, internal DMA, multi-channel and several sample sizes and frame formats. The IP is currently supported for use in ASICs and FPGAs. View see the entire

MIPI C-PHY/D-PHY Combo IP CSI-2 TX+, 3.5Gsps/2.5Gbps The MXL-CDPHY-2p5G-CSI2-TX+-40LP is a high-frequency, low-power, low-cost, source synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.1 and C-PHY v1.2. The PHY can be configured as a MIPI Master supporting camera interface CSI-2. The PHY supports mobile, IoT, virtual reality, and automotive applications. The CSI-2 TX+ is a Mixel proprietary configuration that is optimized to support full-speed production ...

DMA Back-End Core The Northwest Logic DMA Back-End Core from Rambus provides high-performance, scatter-gather DMA operation in a flexible fashion. This enables the core to be easily integrated and used in a wide variety of DMA-based systems. Key features which contribute to this flexibility include: • Works with Northwest Logic soft Expresso Cores and FPGA hard cores • Can be configured with multiple independent DMA Engines which each have their own user interface • Supports P...

Multi-Protocol Engine with Classifier, Look-Aside, 5-10 Gbps The Protocol-IP-196 Multi-Protocol Engine is a protocol-aware packet engine for accelerating IPSec, SSL/TLS, DTLS, 3GPP and MACsec up to 10 Gbps in multi-core application or communication processors offering a large selection of cipher algorithms. Designed for fast integration, maximum CPU offload and offering full transforms, it provides a reliable and cost-effective embedded IP solution that is easy to integrate into multi-core ...

DDR4 Controller Northwest Logic DDR4 Controller Core from Rambus is designed for use in applications requiring high memory throughput, high clock rates and full programmability. The core accepts commands using a simple local interface and translates them to the command sequences required by DDR4 SDRAM devices. The core also performs all initialization, re-fresh and power-down functions. The core uses bank management modules to monitor the status of each SDRAM bank. Banks are only opened...

PHY IP for PCIe Express 4.0 in TSMC N6 The multi-channel DesignWare® PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ demands for higher bandwidth. The PHY provides a cost-effective solution that is designed to meet the needs of today’s high-speed chip-to-chip, board-to-board, and backplane interfaces while being extremely low in power and area. Using leading-edge design, analysis, simulation, and measurement t...

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Fractional-N Frequency Synthesizer PLL (3nm - 180nm) Widely programmable fractional-N delta sigma frequency synthesizer. Low Power/ Low Area hard macro with industry leading jitter performance for its power/area class. Product is currently in mass production from 5nm to 180nm, and ready now in 3nm. Integer-only, DDR/multi-phase, LC and low-jitter ring PLLs also available. View see the entire get in contact with Block Diagram of the Fractional-N Frequency Synthesizer PLL (3nm - ...

RBG DPA resistant cryptographic accelerator core Rambus DPA Resistant Cryptographic Accelerator Core RBG (NRBG+DRBG) prevent against the leakage of secret cryptographic key material through attacks when integrated into an SoC or FPGA. RBG DPA resistant cryptographic accelerator core. The DPA Resistant Hardware cores offer chipmakers an easy-to-integrate technology-independent soft-macro security solution with built-in side-channel resistance for cryptographic functions across a wide array ...

GDDR6 Controller Northwest Logic GDDR6 Controller Core from Rambus is designed for use in applications requiring high memory throughput, high clock rates and full programmability. The core accepts commands using a simple local interface and translates them to the command sequences required by GDDR6 SGRAM devices. The core also performs all initialization, refresh and power-down functions. The core uses bank management techniques to monitor the status of each GDDR6 SGRAM bank (up to 16 ...