INSIDE Secure SM3 Engine The EIP-52 SM3 Engine implements the SM3 hash algorithm. The accelerators include I/O registers, hash calculation cores, message padding logic, and data scheduling logic. Designed for fast integration, low gate count, and maximum performance, the SM3 Engine provides a reliable and cost-effective SM3 IP solution that is easy to integrate into SoC designs. View see the entire get in contact with Sm3 IP
Voltage Optimization Modules Two patented IPs and a design methodology to estimate and track the minimum supply voltage (Vmin) for each individual circuit in the field: TMFLT-S IP (Timing Fault Sensor)
Estimates the Fmax/Vmin of the circuit during a calibration phase TMFLT-R IP (Timing Fault Ring) :
Tracks either the minimum voltage operation (Vmin) or the maximum clock frequency (Fmax) during run-time phase TMFLT Sensor implementation methodology:
Allows choosing the best register candidates to insert TMFLT Sensors. Allowing to minimize the area overhead to less than 2%. View see the entire
Mem Test Analyzer Core The Northwest Logic Mem Test Analyzer Core from Rambus is used to capture the results from Northwest Logic Memory Test Core.
The Mem Test Analyzer Core can be used in conjunction with the Memory Test Core to capture the actual and expected test data. The capture is initiated by an error trigger signal provided by the Memory Test Core. This data can then be retrieved from the Mem Test Analyzer Core via the chip’s configuration & status bus, on-chip processor or dedicated low-pin count serial port.
Rambus also offers easy-to-use scripts, driver and USBI2C bridge board to retrieve and analyze the data captured by the Data Analyzer Core.
AES (ECB), 1 Billion Trace DPA Resistant Cryptographic Accelerator Cores Rambus Crypto Accelerator AES-AE–Fast Hardware Cores offload compute intensive cryptographic algorithms in SoC’s CPU at 100x performance (when run at identical frequencies) and 10% of the power consumption compared to running the same algorithms in software.
The Crypto Accelerator Hardware Cores offer chipmakers an easy-to-integrate technology-independent soft-macro security solution, offering various levels of cryptographic acceleration performance.
They are easy to integrate into various SoC and FPGA architectures and development flows, and are all designed to maximize performance versus silicon area requirements. The Rambus IP core pass all NIST CAVP vectors. Several of the cores are also available in Differential Power Analysis (DPA) protected versions, extensively validated using the standardized Test Vector Leakage Assessment (TVLA) methodology. These Crypto accelerator cores are portable t