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Cadence Accelerates Hyperscale SoC Design with Next-Generati
Cadence Accelerates Hyperscale SoC Design with Next-Generati
Cadence Accelerates Hyperscale SoC Design with Next-Generation 112G Extended Long-Reach SerDes IP on TSMC's N4P Process
Highlights:
DSP-based, flexible-rate SerDes IP is optimized for PPA for next-generation cloud networking, AI/ML, and 5G wireless applications
New architecture delivers exceptional ELR... | April 24, 2023
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