Cadence Tapes Out 16G UCIe Advanced Package IP on TSMC's N3E

Cadence Tapes Out 16G UCIe Advanced Package IP on TSMC's N3E Process Technology – EEJournal

SAN JOSE, Calif., April 24, 2023 — Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the tapeout of Cadence® 16G UCIe™ 2.5D advanced package IP on TSMC’s 3nm (N3E) process technology. Implemented on TSMC’s 3DFabric™ CoWoS-S silicon interposer technology, the IP offers ultra-high bandwidth density, efficient low-power performance and superior low latency, making it ideal for…

Related Keywords

, Debendra Das Sharma , Sanjive Agarwala , Cadence Design Systems Inc , Nasdaq , Express , Ip Group At Cadence , Ucie Consortium , Cadence Design Systems , Cadence Verification , Advanced Package , Intelligent System Design ,

© 2025 Vimarsana