Third-generation 112G-LR SerDes IP Cadence Design Systems has unveiled its third-generation 112G long-reach (112G-LR) SerDes IP on TSMCâs N5 process, targeting hyperscale ASICs, AI/ML accelerators, and switch fabric systems on chip (SoCs). The new architecture offers 25% power savings, 40% area reduction and better design margins over the second-generation architecture, and looks to address the increasing needs for higher performance and power efficiency in modern next-generation cloud data centres. Cadence has enabled different variances of PAM4 SerDes supporting XSR, VSR, MR and LR interconnect standards and through a combination of design wins and collaborations with leading hyperscale and data centre customers, has been able to incorporate specific enhancements in the third-generation product and currently has N5 test chips in-house that are undergoing characterization.