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AMD shows off stacked 3D V-Cache chiplets, resulting in up to 192MB of L3 cache


AMD s 3D V-Cache chiplet tech enters production later this year
on June 1, 2021, 11:15
In brief: AMD caught everyone off guard at Computex 2021 with a demonstration of its new 3D chiplet technology that looks to deliver the type of performance gain you’d typically see with a new process node or microarchitecture.
Developed in collaboration with TSMC, AMD’s first application of the 3D chiplet tech is a vertical cache addition for its high-end processors. In a nutshell, AMD used a process called through-silicon vias (TSVs) to stack additional L3 cache on top of the compute chiplets.
AMD CEO Dr. Lisa Su showed off a prototype Ryzen 5000 CPU with one of two chiplets featuring the added stacked cache. As AnandTech highlights, the difference is obvious compared to the standard chiplet. The 3D V-Cache die is not as large as the core die, so AMD added additional structural silicon for support. Both dies were also thinned, meaning AMD doesn’t hav ....

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