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The In-Chip Monitoring Subsystem from Synopsys (using formerly Moortec technology) allows for a greater understanding of device fabrication, process variability and in-field dynamically changing conditions.
Cadence Design Systems has announced that its PHY and Controller IP for the PCI Express (PCIe) 5.0 specification in the TSMC N7, N6 and N5 process technologies have passed certification tests from PCI-SIG.
SAN JOSE, Calif., June 24, 2022—Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that its PHY and Controller IP for the PCI Express® (PCIe®) 5.0 specification in the TSMC N7, N6 and N5 process technologies have passed certification tests from PCI-SIG® at the industry’s first event for PCIe 5.0 specification compliance held in April. The Cadence® solutions…
Cadence Announces New Low-Power IP for PCI Express 5.0 Specification on TSMC N5 Process Cadence Design Systems, Inc. announced immediate availability of Cadence® IP supporting the PCI Express® (PCIe®) 5.0 specification on TSMC N5 process technology. The next follow-on version on TSMC N3 process technology is expected to be taped out in early 2022. Collaboration with major customers is ongoing for N5 SoC designs targeting hyperscale computing and networking applications. The Cadence IP for PCIe 5.0 technology consists of a ...
Cadence Accelerates Cloud Hyperscale Infrastructure Cadence Design Systems, Inc. announced immediate availability of Cadence® IP supporting the PCI Express® (PCIe®) 5.0 specification on TSMC N5 process technology. The next follow-on version on TSMC N3 process technology is expected to be taped out in early 2022. Collaboration with major customers is ongoing for N5 SoC designs targeting hyperscale computing and networking applications. The Cadence IP for PCIe 5.0 technology consists of a PHY, companion controller and Verif...