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TSS GDDR6 PHY on TSMC 12nm from Openedges

TSS GDDR6 PHY on TSMC 12nm from Openedges
The GDDR6 OPHY utilizes state-of-the-art architecture in full custom analog mixed-signal design to overcome the problem of long-term impedance drift and clock phase drift, allowing impedance and clock phase updates without the need to interrupt data traffic. The programmable timing PHY boundary combines flexibility with analog precision, and the result is ultra low PHY read/write latency between OMC and the GDDR6 DRAM without sacrificing performance.
At the system level, the GDDR6 OPHY was designed with minimal package substrate layer and PCB layer count in mind. This enables the integration of a GDDR6 memory sub-system solution in cost sensitive applications, such as consumer edge devices, AI, GPU, HPC, STB, SSD controllers, and application processors. ....

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GDDR6 PHY&Controller Samsung 10/8LPP IP Core

GDDR6 PHY&Controller Samsung 10/8LPP
The Innosilicon GDDR6 PHY is the world’s first silicon proven commercial GDDR6 IP, which is fully compliant with the JEDEC GDDR6 (JESD250) standard, supporting up to 16Gbps per pin. The GDDR6 interface supports 2 channels, each with 16bits for a total data width of 32bits. With speed up to 16Gbps per pin, the Innosilicon GDDR6 PHY offers a maximum bandwidth of up to 64GB/s. And, the Innosilicon GDDR6X PHY uses four-level pulse amplitude modulation (PAM4) signaling to extract more efficiency and higher data rates, which will be available in advanced FinFET nodes for leading-edge customer integration. ....

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