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Return to growth

Industrial output set to rebound in next few months ....

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MIPI D-PHY Receiver in TSMC 65nm LP

The MIPI D-PHY Receiver is a high-frequency low-power, low-cost, sourcesynchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display interface applications (DSI). ....

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MIPI D-PHY Transmitter - Designed for TSMC 40nmLP

The MXL-DPHY-CSI2-TX-T-40LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for . ....

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MIPI Soundwire PHY IP Core

The physical layer block implements all the line-side functions such as NRZI encoding & decoding, bus clash detection, data line buffer enable/disable. . ....

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MIPI D-PHY Transmitter/Receiver - Designed for TSMC 28nm

The MXL-PHY-MIPI-UNIVERSAL-T-028 is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. ....

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