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Ultra-Fast Baseline and Extended JPEG Decoder Core This JPEG decompression IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG decoder that handles extremely high pixel rates. The JPEG-DX-F Decoder decompresses JPEG images and the video payload for Motion-JPEG container formats. It accepts compressed streams of images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats. Depending on its configu...

DPA Resistant Cryptographic Accelerator Core ChaCha20 – Fast Rambus DPA Resistant Hardware Cores prevent against the leakage of secret cryptographic key material through attacks when integrated into an SoC or FPGA. ChaCha 20 Fast DPA resistant cryptographic accelerator core. The DPA Resistant Hardware cores offer chipmakers an easy-to-integrate technology-independent soft-macro security solution with built-in side-channel resistance for cryptographic functions across a wide array of devices. These high-performance cores provide a higher level of protection than standard security cor...

AES Key Wrap Accelerator The EIP-37 is the IP for accelerating the AES Key Wrap cipher algorithm (NIST-Key-Wrap & RFC3394). Designed for fast integration, low gate count and full transforms, the EP-37 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into SoCs that need high speed key wrap and (key) storage or key import and export systems View see the entire get in contact with AES IP

INSIDE Secure SM3 Engine The EIP-52 SM3 Engine implements the SM3 hash algorithm. The accelerators include I/O registers, hash calculation cores, message padding logic, and data scheduling logic. Designed for fast integration, low gate count, and maximum performance, the SM3 Engine provides a reliable and cost-effective SM3 IP solution that is easy to integrate into SoC designs. View see the entire get in contact with Sm3 IP

Camellia Accelerator The Camellia Engine implements the Camellia crypto algorithm, as specified in “Specification of Camellia” and RFC3713. Designed for fast integration, low gate count, and maximum performance, the IP Camellia Engine provides a reliable and cost-effective Camellia IP solution that is easy to integrate into SoC designs. View see the entire get in contact with © 2021 Design And Reuse All Rights Reserved. No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse. Partne...