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Cadence Extends Collaboration with TSMC and Microsoft to Advance Giga-Scale Physical Verification in the Cloud

Highlights: • Enables customers to effectively leverage the Cadence Pegasus Verification System and TSMC technology on the Microsoft Azure cloud with the Cadence CloudBurst Platform • Initial results demonstrated that the Cadence Pegasus Verification System in the cloud provided optimal performance and reduced cloud compute costs by more than 20% SAN JOSE, Calif., April 17,…
Santa Clara Dan Kochpatcharin Chin Chi Teng Mujtaba Hamid Cloud Alliance Cadence Design Systems Inc

Synopsys.ai Unveiled as Industry's First Full-Stack, AI-Driven EDA Suite for Chipmakers – EEJournal

Key Highlights: Synopsys.ai provides AI-driven solutions for chip design, with digital and analog, verification, test and manufacturing components. AI engines significantly boost engineering productivity and silicon quality while minimizing costs. NVIDIA, TSMC, IBM, MediaTek and Renesas all support Synopsys' AI-driven EDA design strategy with significant benefits already being seen: Renesas achieved a 10x improvement in…
Patrick Moorhead Takahiro Ikenobe Dan Kochpatcharin Vivekk Singh Shankar Krishnamoorthy Global Semiconductor

Synopsys Accelerates Multi-Die System Designs With Successful UCIe PHY IP Tape-Out on TSMC N3E Process

As Synopsys and TSMC collaborate to deliver high-quality IP on TSMC’s advanced FinFET processes, Synopsys announces a successful tape-out of the Universal ...
Debendra Das Sharma Dan Kochpatcharin Ucie Consortium Design Infrastructure Management Division Universal Chiplet Interconnect Express Ucie Phy Ip Tape Out On Tsmc N3e Process

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New Electronics - Cadence automates custom/analogue design migration on TSMC advanced technologies

Cadence Design Systems, working with TSMC, has developed a node-to-node design migration flow built upon its Virtuoso design platform for custom/analogue IC blocks that use TSMC’s advanced process technologies.
Tom Beckley Dan Kochpatcharin Head Of Design Infrastructure Management Division System Analysis Group Application Library Environment Virtuoso Schematic Editor

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