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INSIDE Secure SM4 Engine The EIP-12 SM4 Engine implements the SM4 cipher block algorithm. The accelerator includes I/O registers, encryption and decryption cores. Designed for fast integration, low gate count, and maximum performance, the SM4 Engine provides a reliable and cost-effective SM4 IP solution that is easy to integrate into SoC designs. View see the entire get in contact with SM4 IP

Custom Regulated High Capacity Charge Pump The CC-301IP is a variable Frequency, Regulated High Capacity Charge Pump which can be utilized as a supply booster (single stage +5% to +20%) of a given Supply voltage for on-chip component (op amp, ADC, DAC, Comparator, etc) headroom extension, enhancing the rail to rail performance of on chip components. The CC-301IP Charge Pump range can be extended to create a +40V to +100V on chip generated High Voltage supply for MEMS or Haptic Circuits. Th...

CAN is a message-based protocol, designed specifically for automotive applications and as of now, for any avionics equipment in safety critical applications. ...

The WEA9S22 is a complete 24 bits Fractional-N microwave synthesizer able to synthesize frequencies from 7 GHz to 9 GHz with the integrated VCO. It consists ...

The performance leading INNOSILICON DDR PHY supports DDR5/LPDDR5 DDR4/LPDDR4/DDR3/LPDDR3/DDR2/LPDDR2/DDR at speeds up to 6400Mb/s and in any bus width. ...

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Multi-Port Front-End The Northwest Logic Multi-Port Front-End Core from Rambus provides a multi-port interface to Northwest Logic Memory Controller Cores. Each user request is provided with its own request priority. The arbiter selects requests based on priority and then round robin arbitration. The arbiter can also perform Quality Of Service (QOS) based arbitration. In this mode, the arbitration results in each port receiving a specified amount of memory bandwidth. Each port al...

RT-630 Programmable Root-of-Trust Security Processor for Cloud/AI/ML SoC FIPS-140 Rambus Hardware Root of Trust RT-630 is a fully-programmable hardware security core offering security by design. It protects against a wide range of attacks through state-of-the-art anti-tamper and security techniques. As cloud, artificial intelligence, and machine learning applications evolve, device architects are understandably concerned about emerging security threats. While these applications may differ...

TESIC CC EAL5+ Secure Element IP Core TESIC is a CC EAL5+ PP0084 proven/certification-ready secure element IP that is delivered as hard macro for plug-and-play System-on Chip (SoC) integration View see the entire get in contact with Block Diagram of the TESIC CC EAL5+ Secure Element IP Core secure element IP

GDDR6 PHY&Controller Samsung 10/8LPP The Innosilicon GDDR6 PHY is the world’s first silicon proven commercial GDDR6 IP, which is fully compliant with the JEDEC GDDR6 (JESD250) standard, supporting up to 16Gbps per pin. The GDDR6 interface supports 2 channels, each with 16bits for a total data width of 32bits. With speed up to 16Gbps per pin, the Innosilicon GDDR6 PHY offers a maximum bandwidth of up to 64GB/s. And, the Innosilicon GDDR6X PHY uses four-level pulse amplitude modulation (PAM...