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Reorder Core The Reorder Core from Rambus reorders requests based on first on priority and second on throughput optimization. Throughput optimization includes moving same bank/same row requests next to each other, same bank/ different row requests away from each other, moving reads next to reads and write next to writes. The core can be used to optionally enforce data coherency by preventing any same row requests from passing over each other. The core can also optionally disable intra...

High Performance DDR4/3 Memory Controller Mobiveils DDR4/3 Memory Controller is a highly flexible and configurable design targeted for high performance enterprise server and real-time consumer applications that utilize computational elements like graphics controllers, general purpose, digital signal processors, etc. The controller architecture is carefully tailored to achieve reliable high-frequency operation, dynamic power management, error injection and support for rapid system debug. D...

DVB-S2X WideBand Demodulator IP This is a high-performance, dual high-symbol-rate (HSR) DVB-S2/S2X demodulator IP extarcted from production chipsets with integrated tuner and silcon proven technology. The demodulators are compliant with Annex M of the DVB-S2 specification EN 302 307 and can demodulate signals up to 500 Msymbol/s. Each HSR demodulator may demodulate up to 2 slices. This implements 8 multi-standard demodulators capable of DVB-S, DTV legacy, DVB-S2 and DVB-S2X broadcast-profi...

RT-660 DPA-Resistant Programmable Root-of-Trust Security Processor for Govt/Aero/Defense FIPS-140 Rambus Hardware Root of Trust RT-660 is a fully-programmable hardware security core offering security by design. It protects against a wide range of attacks through state-of-the-art anti-tamper and security techniques. Government hardware most often requires higher security protections due to sensitive information being stored or processed. As with every product within the CryptoManager Root ...

Body bias voltage generator - GLOBALFOUNDRIES 22FDX The Racyics® ABX Generator IP is a body bias voltage generator for the Racyics® ABX Platform for GLOBALFOUNDRIES 22FDX® technology. It contains a closed loop body bias regulation loop to generate N-well and P-well bias voltages for adaptive compensation of process, voltage and temperature (PVT) variations during device operation. View see the entire get in contact with Body bias voltage IP

Ultra-Fast Baseline and Extended JPEG Decoder Core This JPEG decompression IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG decoder that handles extremely high pixel rates. The JPEG-DX-F Decoder decompresses JPEG images and the video payload for Motion-JPEG container formats. It accepts compressed streams of images with 8- or 12-bit color samples and ...

DPA Resistant Cryptographic Accelerator Core ChaCha20 – Fast Rambus DPA Resistant Hardware Cores prevent against the leakage of secret cryptographic key material through attacks when integrated into an SoC or FPGA. ChaCha 20 Fast DPA resistant cryptographic accelerator core. The DPA Resistant Hardware cores offer chipmakers an easy-to-integrate technology-independent soft-macro security solution with built-in side-channel resistance for cryptographic functions across a wide array of dev...

AES Key Wrap Accelerator The EIP-37 is the IP for accelerating the AES Key Wrap cipher algorithm (NIST-Key-Wrap & RFC3394). Designed for fast integration, low gate count and full transforms, the EP-37 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into SoCs that need high speed key wrap and (key) storage or key import and export systems View see the entire get in contact with AES IP

INSIDE Secure SM3 Engine The EIP-52 SM3 Engine implements the SM3 hash algorithm. The accelerators include I/O registers, hash calculation cores, message padding logic, and data scheduling logic. Designed for fast integration, low gate count, and maximum performance, the SM3 Engine provides a reliable and cost-effective SM3 IP solution that is easy to integrate into SoC designs. View see the entire get in contact with Sm3 IP

Camellia Accelerator The Camellia Engine implements the Camellia crypto algorithm, as specified in “Specification of Camellia” and RFC3713. Designed for fast integration, low gate count, and maximum performance, the IP Camellia Engine provides a reliable and cost-effective Camellia IP solution that is easy to integrate into SoC designs. View see the entire get in contact with © 2021 Design And Reuse All Rights Reserved. No portion of this site may be copied, retransmitted, repos...