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CAN 2.0, CAN FD & CAN-XL Bus Controller Implements a CAN bus controller that performs serial communication according to the CAN 2.0, CAN FD, and CAN XL specifications. It supports the original Bosch protocol and ISO specifications as defined in ISO 11898—including time-triggered operation (TTCAN) as specified in ISO 19898-4—and is also optimized to support the popular AUTOSAR and SAE J1939 specifications. The CAN protocol uses a multi-master bus configuration for the transfer of frame...

USB3.x Gen2 Retimer Controller Softnautics USB3.x Retimer softcore is designed for use USB Port/Cable Retimer applications with USB SuperSpeedPlus/SuperSpeed link operations The IP has been verified in simulation and is synthesis clean for FPGA implementations. The core is highly power efficient for port or cable retimer applications View see the entire get in contact with © 2021 Design And Reuse All Rights Reserved. No portion of this site may be copied, retransmitted, reposted, du...

High-performance PCIe-AXI Bridge and/or scatter-gather DMA The Northwest Logic Expresso DMA Bridge Core from Rambus provides high-performance DMA and/or bridging between PCI Express and AXI for both Endpoint and Root Port applications. Key features include: DMA operation hard cores • Supports memory-mapped/streaming (FIFO) DMA operation • Can be configured with multiple DMA Channels which are independently controlled by software • Supports legacy, MSI, MSI-X and local A...

The Rambus FIPS Security Toolkit (formerly from Inside Secure) is a complete cryptographic security solution for IoT providing the tools required to secure ...

The S3ADSIQ80M12BC22ULP is an ultra low power 12-bit dual-channel High-Speed SAR ADC IP. This IP includes two ADC channels sampling up-to 80MS/s including Voltage Reference Buffers. It features an excellent dynamic performance including 75.0dB SFDR, 63.5dB SNR and 10.2-bit ENOB. It also features an excellent cross-channel performance with ±0.1dB Gain Mismatch and -75.0dB Crosstalk. This high-end performance is obtained with a compact die area and an ultra low total power for the full ...

Dual-Core HEVC, AV1 & H.264, AVS2, VP9 Combined Decoder The WAVE537 is a dual-core decoder IP, architected for decoding video to 8K60fps(900MHz) in HEVC/H.265, AVC/H.264, VP9, AVS2, AV1 standard formats in real-time with the most optimized size and stable decoding performance. The WAVE537 is cost-effective as it is architected to pick out and reuse sharable blocks from various codec standards and apply them to the common blocks, in which the IP architecture becomes streamlined with minim...

PCI Express Gen1/Gen2/Gen3 Hybrid Controller with SRIOV Support The PCI Express Hybrid (RC and EP) Controller is a highly flexible and configurable design targeted for end-point implementations in desktop, server, mobile, networking and telecom applications. The controller architecture is carefully tailored to optimize link utilization, latency, reliability, power consumption, and silicon footprint. The PCI Express Hybrid (RC and EP) Controller is part of the PCI-Express (GPEX) family o...

Read-Modify-Write Core The Read-Modify-Write (RMW) Core from Rambus handles misaligned bursts when an Error Correction Code (ECC) is being used. An ECC code word must be calculated over an entire data word. Misaligned bursts can have partial data words at the front and back end of the burst. To calculate the correct ECC code word, the Read-Modify-Write Core forms the correct starting and ending data words by reading the existing data words and combining them appropriately with the new par...

Ethernet MAC 10G/25G Comcores Ethernet MAC 10G/25G provides a complete IEEE 802.3 Ethernet Layer 2 solution. The MAC IP core performs the Link function of the 10G/25G Ethernet Standard and is a low latency cut-through implementation reaching best in market results while still keeping size at a minimum. The core is fully configurable and is prepared for IEEE1588 integration and easy interfacing with Comcores 10G/25G PCS solution. The Ethernet MAC Core, on the Client side, implements a 64...

eFPGA IP cores for GF 22FDX The EFLX®4K Logic IP core is an embeddable FPGA IP core containing 2,520 Look-Up-Tables (LUTs: each is 6-input, or dual-5-input, with 2 independent outputs with 2 bypassable flip flops) in Reconfigurable Building Blocks (RBBs) and 21 Kbit RAM, an improved XFLX™ interconnect network, multiple clocks & scan: fully reconfigurable in-field at any time. The EFLX 4K DSP core has 40 DSP MACs (22x22 multiplier with 48 bit accumulator). In the Gen2 architecture, MACs...