Ashling RiscFree now supports Andes Technology RISC-V CPUs

Ashling and Andes Technology announced today that Ashling’s RiscFree™ Toolchain will be extended to support the broad range of Andes RISC-V CPU IPs including support for the AndeStar™ V5 Performance and CoDense™ ISA Extension.

Related Keywords

California ,United States ,Ireland ,Chennai ,Tamil Nadu ,India ,San Francisco ,America ,Hugh Okeeffe ,Charlie Su ,Asia Pacific ,Ashling Riscfree ,Andes Riscv Cpus ,Nadim Shehayed ,Development Tools Services ,Ashling Integrated Development Environment ,Andes Technology ,Integrated Development Environment ,Different Cores ,One Solution ,Hugho Keeffe ,Managing Director ,Andes Technology President ,Embedded Development Tools ,Limerick Ireland ,Chennai India ,Middle East ,Trace Probes ,Power Architecture ,Ashling ,Iscfree , ,Andes ,Risc V ,Pu ,