February 22, 2021
CEA-Leti & Dolphin Design Report FD-SOI Breakthrough that Boosts Operating Frequency by 450% and Reduces Power Consumption by 30%
Joint Paper Presented at ISSCC 2021 Shows How New Adaptive Back-Biasing Technique Overcomes Integration Limits in Chip Design Flows
GRENOBLE, France – Feb. 22, 2021 – CEA-Leti and Dolphin Design have developed an adaptive back-biasing (ABB) architecture for FD-SOI chips that can be seamlessly integrated in the digital design flow with industrial-grade qualification, overcoming integration drawbacks of existing ABB techniques.
Fully Depleted Silicon on Insulator (FD-SOI) is a technology that allows the biasing of the transistor’s body that acts as a back gate. Unlike conventional bulk technology, FD-SOI enables a wide voltage range of the body bias. This permits compensating for process, voltage, and temperature (PVT) variations by controlling the threshold voltage. For example, in switch operations, when the switch is on, the body bias is changed to reduce the on-resistance by reducing threshold voltage and allowing more current to pass. That accelerates the circuit. In the off state, the body bias is changed to raise the off-resistance by increasing the threshold voltage, consequently reducing the leakage current. This shows that FD-SOI technology can be used either to accelerate the design or reduce the leakage power.