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The SM3 hash algorithm is a cryptographic hash function designed by the Chinese Commercial Cryptography Administration Office (CCCAO) in order to propose ...
Tunable DES - Triple DES (ECB, CBC, CTR) accelerator - optional SCA protection The Data Encryption Standard (DES) is defined in FIPS PUB 46-3 as a symmetric-key algorithm. The triple DES (TDES) is block cipher that applies the DES algorithm three times to each data block. The TDES is defined in ANS X9.52-1998, NIST SP 800-67 rev-1 and ISO/IEC 18033-3:2010. TDES is a symmetric-key algorithm, meaning the same key is used for both encrypting and decrypting. View see the entire get in contact with Cryptography IP
Multi Protocol IO Concentrator (RDC) IP Core for Safe and Secure Ethernet Network Our IP Core is the ideal solution to link all your equipment, sensor or actuator whatever the used protocol to an Avionic network in a safe & secure manner. It brings a high performance, low latency, safe and cyber-secure link between your equipment and the Avionic network based on ARINC664p7/Ethernet network. On the Avionic network side, CetraC technology is fully compliant with ARINC664 Part 7 and Ethernet standards. It allows both cyclic and event-driven communications in full duplex. A 100% hardware solution with embedded redundancy management feature to increase network reliability.
Device Secure Debug The Joint Test Action Group (JTAG) is the IEEE1149.1 Standard Test Access Port (TAP) and Boundary Scan Architecture. Giving a full access to the internal system components of the device, the TAP interface can be a backdoor for hackers. Secure-IC offers a set of tools to secure the access to the device. This solution can be deployed in the Securyzr iSE or as a standalone IP. View see the entire
Multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC) CoMira’s multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC) is fully configurable and programmable to support “any rate on any channel” (400G/200G/100G/50G/25G/10G/1G). It uses a novel time-sliced architecture that affords maximum density for high port count applications while maintaining industry-leading latencies that are optimized for data center applications. In addition to being compliant with the IEEE 802.3bs, IEEE 802.3-2012, 25G/50G Ethernet Consortium, IEEE 802.3by, and OIF Flex-E Standards, CoMira also offers non-standard and application-driven protocols and modes of operation that allow us to tailor each IP configuration to a customer’s specific needs. This, in turn, lets them better differentiate their own end products.
MIPI D-PHY Universal Tx / Rx v1.1 @1.5ghz Ultra Low Power for IoT & Wearables Arasan 2nd Generation MIPI D-PHY v1.1 IP supporting speeds of up to 1.5 Gbps on TSMC 22nm process technology for SoC designs. Arasan’s D-PHY IP is available on both TSMC’s industry-leading 22nm ultra-low power (22ULP) and 22nm ultra-low leakage (22ULL) process technologies. TSMC 22nm ultra-low power (22ULP) is an ideal foundry technology for applications including image processing, digital TVs, set-top boxes, smartphones and consumer products in terms of its power, performance and area (PPA) optimization, while its 22nm ultra-low leakage (22ULL) technology provides significant power reduction to support IoT and wearable device applications, where power is of paramount importance.
Galois Field based Reed Solomon Codec Reed Solomon FEC Error Correcting Code Based on Galois Field Arithmetic If RS is configured for 16 bits of error correction, then the same decoder/encoder can be used for any number of bit corrections from 1 to 15 This way the overhead can be reduced if desired. View see the entire get in contact with Reed Solomon FEC Error Correction IP
Tunable SM4 (ECB, CBC, CTR, XTS, CCM, GCM) accelerator - optional SCA protection SM4 is a standardized block cipher used in the Chinese National Standard for Wireless LAN WAPI (Wired Authentication and Privacy Infrastructure). View see the entire get in contact with Cryptography IP
integrated Secure Element (iSE) for multiple applications - Hardware Security Module (HSM) - Security Enclave - Security Subsystem As part of Secure-IC s iSSP (integrated Security Service Platform), Secure-IC is able to provide integrated Secure Elements (iSE) that can act as trust anchors that protect the security assets of a device. An iSE - also referred as HSM or Security Subsystem or Root of Trust - is an IP block that can be embedded into every device to ensure security services such as key management, lifecycle management, Secure Boot & updates Secure-ICâs Securyzr provides the core security services required to build a security architecture for a wide variety of devices and connected objects: mobile, payment device, smart card, ECU, Set-Top-Box, and HSM.
FEC As serial link speeds have increased, the reach achievable has become more and more limited by the lossy nature of the physical media which introduces the need for forward error correction (FEC) methods in the data-recovery functionality of Ethernet port logic. Starting at 10G line rates, Firecode was introduced into the 802.3 Ethernet Standard. The 802.3bj IEEE draft approved in June of 2014 introduced the Reed Solomon FEC algorithm for higher speed backplane and copper links. CoMira provides a complete family of FEC cores for use in Ethernet (100G/50G/40G/25G/10G) and other applications. These cores may be purchased standalone, or as a configurable option of the CoMira UMAC IP. CoMira FEC IP is designed using a similar architecture employed in the UMAC to facilitate seamless integration of the former into the latter.